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14-bit, 500 ksps pulsar adc in msop ad7946 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2005C2007 analog devices, inc. all rights reserved. features 14-bit resolution with no missing codes throughput: 500 ksps inl: 0.4 lsb typical, 1 lsb maximum (0.0061% of fsr) sinad: 85 db @ 20 khz thd: ?100 db @ 20 khz pseudo differential analog input range 0 v to ref with ref up to vdd no pipeline delay single-supply 5 v operation with 1.8 v/2.5 v/3 v/5 v logic interface serial interface, spi/qspi/microwire?/dsp compatible daisy-chain multiple adcs and busy indicator power dissipation 3.3 mw @ 5 v/100 ksps 3.3 w @ 5 v/100 sps standby current: 1 na 10-lead msop (msop-8 size) and 3 mm 3 mm qfn (lfcsp) (sot-23 size) pin-for-pin compatible with the 16-bit ad7686 applications battery-powered equipment data acquisition instrumentation medical instruments process control application diagram ad7946 ref gnd vdd in+ in? vio sdi sck sdo cnv 1.8v to vdd 3- or 4-wire interface (spi, daisy chain, cs) 0.5 v to 5v 5 v 0v to ref 04656-001 figure 1. general description the ad7946 is a 14-bit, charge redistribution, successive approximation, analog-to-digital converter (adc) that operates from a single 5 v power supply, vdd. it contains a low power, high speed, 14-bit sampling adc with no missing codes, an internal conversion clock, and a versatile serial interface port. the part also contains a low noise, wide bandwidth, short aperture delay track-and-hold circuit. on the cnv rising edge, it samples an analog input in+ between 0 v to ref with respect to a ground sense in?. the reference voltage, ref, is applied externally and can be set up to the supply voltage. its power scales linearly with throughput. the spi-compatible serial interface also features the ability, using the sdi input, to daisy-chain several adcs on a single, 3-wire bus, or it provides an optional busy indicator. it is compatible with 1.8 v, 2.5 v, 3 v, or 5 v logic, using the separate supply vio. the ad7946 is housed in a 10-lead msop or a 10-lead qfn (lfcsp) with operation specified from ?40c to +85c. table 1. msop, qfn (lfcsp) 14-/16-/18-bit pulsar? adc type 100 ksps 250 ksps 400 ksps to 500 ksps 1000 ksps adc driver 14-bit ad7940 ad7942 1 ad7946 1 16-bit ad7680 ad7685 1 ad7686 1 ad7980 1 ada4941 ad7683 ad7687 1 ad7688 1 ad7983 1 ada4841 ad7684 ad7694 ad7693 1 18-bit ad7691 1 ad7690 1 ad7982 1 ada4941 ad7984 1 ada4841 1 pin-for-pin compatible.
ad7946 rev. a | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 application diagram ........................................................................ 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configurations and function descriptions ........................... 7 typical performance characteristics ............................................. 8 ter mi nolo g y .................................................................................... 11 theory of operation ...................................................................... 12 circuit information .................................................................... 12 converter operation .................................................................. 12 typical connection diagram ................................................... 13 analog input ............................................................................... 13 driver amplifier choice ............................................................ 14 voltage reference input ............................................................ 14 power supply ............................................................................... 15 supplying the adc from the reference .................................. 15 single-supply application ......................................................... 15 digital interface .......................................................................... 16 cs mode 3-wire, no busy indicator .................................. 17 cs mode 3-wire with busy indicator ................................... 18 cs mode 4-wire, no busy indicator ..................................... 19 cs mode 4-wire with busy indicator ................................... 20 chain mode, no busy indicator ............................................ 21 chain mode with busy indicator ........................................... 22 application guidelines .................................................................. 23 layout .......................................................................................... 23 evaluating the ad7946s performance .................................... 23 outline dimensions ....................................................................... 24 ordering guide .......................................................................... 24 revision history 12/07rev. 0 to rev. a qfn package available......................................................universal changes to table 1............................................................................ 1 changes to table 5............................................................................ 6 changes to ordering guide .......................................................... 24 7/05revision 0: initial version
ad7946 rev. a | page 3 of 24 specifications vdd = 4.5 v to 5.5 v, vio = 2.3 v to vdd, ref = vdd, t a = ?40c to +85c, unless otherwise noted. table 2. parameter conditions min typ max unit resolution 14 bits analog input voltage range in+ ? in? 0 ref v absolute input voltage in+ ?0.1 vdd + 0.1 v in? ?0.1 0.1 v analog input cmrr f in = 200 khz 65 db leakage current at 25c acquisition phase 1 na input impedance see the analog input section accuracy no missing codes 14 bits differential linearity error ?0.7 0.3 +0.7 lsb 1 integral linearity error ?1 0.4 +1 lsb transition noise ref = vdd = 5 v 0.33 lsb gain error 2 , t min to t max 0.3 6 lsb gain error temperature drift 1 ppm/c offset error 2 , t min to t max 0.3 6 lsb offset temperature drift 1 ppm/c power supply sensitivity vdd = 5 v 5% 0.1 lsb throughput conversion rate 0 500 ksps transient response full-scale step 400 ns ac accuracy signal-to-noise f in = 20 khz, ref = 5 v 84.5 85 db 3 f in = 20 khz, ref = 2.5 v 84 db spurious-free dynamic range f in = 20 khz ?100 db total harmonic distortion f in = 20 khz ?100 db signal-to-(noise + distortion) f in = 20 khz, ref = 5 v 84.5 85 db f in = 20 khz, ref = 5 v, ?60 db input 25 db intermodulation distortion 4 100 db 1 lsb means least significant bit. with the 5 v input range, one lsb is 305.2 v. 2 see the terminology section. these specific ations do include full temperature range variation but do not include the error con tribution from the external reference. 3 all specifications in db are referred to a full-scale input, fs. tested with an input signal at 0.5 db below full scale, unles s otherwise specified. 4 f in1 = 21.4 khz, f in2 = 18.9 khz, each tone at ?7 db below full scale.
ad7946 rev. a | page 4 of 24 vdd = 4.5 v to 5.5 v, vio = 2.3 v to vdd, ref = vdd, t a = ?40c to +85c, unless otherwise noted. table 3. parameter conditions min typ max unit reference voltage range 0.5 vdd + 0.3 v load current 500 ksps, ref = 5 v 100 a sampling dynamics ?3 db input bandwidth 9 mhz aperture delay vdd = 5 v 2.5 ns digital inputs logic levels v il ?0.3 0.3 vio v v ih 0.7 vio vio + 0.3 v i il ?1 +1 a i ih ?1 +1 a digital outputs data format serial 14-bits straight binary pipeline delay conversion results available immediately after completed conversion v ol i sink = +500 a 0.4 v v oh i source = ?500 a vio ? 0.3 v power supplies vdd specified performance 4.5 5.5 v vio specified performance 2.3 vdd + 0.3 v vio range 1.8 vdd + 0.3 v standby current 1 , 2 vdd and vio = 5 v, 25c 1 50 na power dissipation vdd = 5 v, 100 sps throughput 3.3 w vdd = 5 v, 100 ksps throughput 3.3 3.8 mw vdd = 5 v, 500 ksps throughput 19 mw temperature range 3 specified performance t min to t max ?40 +85 c 1 with all digital inputs forced to vio or gnd as required. 2 during acquisition phase. 3 contact sales for extended the temperature range.
ad7946 rev. a | page 5 of 24 timing specifications t a = ?40c to +85c, vdd = 4.5 v to 5.5 v, vio = 2.3 v to 5.5 v or vdd + 0.3 v, whichever is the lowest, unless otherwise stated. see figure 2 and figure 3 for load conditions. table 4. parameter symbol min typ max unit conversion time: cnv rising edge to data available t conv 0.5 1.6 s acquisition time t acq 400 ns time between conversions t cyc 2 s cnv pulse width ( cs mode) t cnvh 10 ns sck period ( cs mode) t sck 15 ns sck period (chain mode) t sck vio above 4.5 v 17 ns vio above 3 v 18 ns vio above 2.7 v 19 ns vio above 2.3 v 20 ns sck low time t sckl 7 ns sck high time t sckh 7 ns sck falling edge to data remains valid t hsdo 5 ns sck falling edge to data valid delay t dsdo vio above 4.5 v 14 ns vio above 3 v 15 ns vio above 2.7 v 16 ns vio above 2.3 v 17 ns cnv or sdi low to sdo d15 msb valid ( cs mode) t en vio above 4.5 v 15 ns vio above 2.7 v 18 ns vio above 2.3 v 22 ns cnv or sdi high or last sck falling edge to sdo high impedance ( cs mode) t dis 25 ns sdi valid setup time from cnv rising edge ( cs mode) t ssdicnv 15 ns sdi valid hold time from cnv rising edge ( cs mode) t hsdicnv 0 ns sck valid setup time from cnv rising edge (chain mode) t ssckcnv 5 ns sck valid hold time from cnv rising edge (chain mode) t hsckcnv 5 ns sdi valid setup time from sck falling edge (chain mode) t ssdisck 3 ns sdi valid hold time from sck falling edge (chain mode) t hsdisck 4 ns sdi high to sdo high (chain mode with busy indicator) t dsdosdi vio above 4.5 v 15 ns vio above 2.3 v 26 ns
ad7946 rev. a | page 6 of 24 absolute maximum ratings table 5. parameter rating analog inputs in+ 1 , in? 1 gnd ? 0.3 v to vdd + 0.3 v or 130 ma ref gnd ? 0.3 v to vdd + 0.3 v supply voltages vdd, vio to gnd ?0.3 v to +7 v vdd to vio 7 v digital inputs to gnd ?0.3 v to vio + 0.3 v digital outputs to gnd ?0.3 v to vio + 0.3 v storage temperature range ?65c to +150c junction temperature 150c ja thermal impedance 10-lead msop 200c/w 10-lead qfn 48.7c/w jc thermal impedance 10-lead msop 44c/w 10-lead qfn 2.96c/w lead temperature vapor phase (60 sec) 215c infrared (15 sec) 220c 1 see the analog input section. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution 04656-002 500a i ol 500a i oh 1.4 v to sdo c l 50pf figure 2. load circuit fo r digital interface timing 04656-003 30% vio 70% ovdd 2v or vio ? 0.5v 1 0.8v or 0.5v 2 0.8v or 0.5v 2 2v or ovdd ? 0.5v 1 t delay t delay notes 1 2v if vio above 2.5v, vio ? 0.5v if vio below 2.5v. 2 0.8v if vio above 2.5v, 0.5v if vio below 2.5v. figure 3. voltage levels for timing
ad7946 rev. a | page 7 of 24 pin configurations and function descriptions 04656-004 ref vdd in+ in? gnd vio sdi sck sdo cnv 1 2 3 4 5 10 9 8 7 6 ad7946 top view (not to scale) figure 4. 10-lead msop pin configuration 04656-005 ref vdd in+ in? gnd vio sdi sck sdo cnv ad7946 top view (not to scale) 1 2 3 4 5 10 9 8 7 6 figure 5. 10-lead qfn (lfcsp) pin configuration table 6. pin function descriptions pin no. mnemonic type 1 description 1 ref ai reference input voltage. the ref range is from 0.5 v to vdd, and is referred to the gnd pin. this pin should be decoupled closely to the pin with a 10 f capacitor. 2 vdd p power supply. 3 in+ ai analog input. it is referred to in?. the voltage range, that is, the difference between in+ and in?, is 0 v to ref. 4 in? ai analog input ground sense. connect to the analog ground plane or to a remote sense ground. 5 gnd p power supply ground. 6 cnv di convert input. this input has multiple functions. on its leading edge, it initiates the conversions and selects the interface mode, chain, or cs . in cs mode, it enables the sdo pin when low. in chain mode, the data should be read when cnv is high. 7 sdo do serial data output. the conversion result is output on this pin. it is synchronized to sck. 8 sck di serial data clock input. when the part is selected, the conversion result is shifted out by this clock. 9 sdi di serial data input. this input provides multiple features. it selects the interface mode of the adc as follows: chain mode is selected if sdi is low during the cnv rising edge. in this mode, sdi is used as a data input to daisy-chain the conversion results of two or more adcs onto a single sdo line. the digital data level on sdi is output on sdo with a delay of 14 sck cycles. cs mode is selected if sdi is high during the cnv rising edge. in this mode, either sdi or cnv can enable the serial output signals when low, and if sdi or cnv is low when the conversion is complete, the busy indicator feature is enabled. 10 vio p input/output interface digital power. nominally at the sa me supply as the host interface (1.8 v, 2.5 v, 3 v, or 5 v). 1 ai = analog input, di = digital input, do = digital output, and p = power.
ad7946 rev. a | page 8 of 24 typical performance characteristics code inl (lsb) 04656-006 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 0 4096 8192 12288 16384 positive inl = +0.17lsb negative inl = ?0.26lsb figure 6. integral nonlinearity vs. code 04656-046 0 50000 100000 150000 200000 250000 300000 2009 200a 200b 200c 200d 200e 200f code in hex counts 000 0 261120 00 vdd = ref = 5v figure 7. histogram of a dc input at the code center frequency (khz) amplitude (db of full scale) 04656-008 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 0 20 40 60 80 100 120 140 160 180 200 220 240 8192 point fft vdd = ref = 5v f s = 500ksps f in = 20.14khz snr = 85.3db thd = ?105.2db second harmonic = ?106db third harmonic = ?110db figure 8. fft plot code dnl (lsb) 04656-009 positive dnl = +0.20lsb negative dnl = ?0.13lsb 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 0 4096 8192 12288 16384 figure 9. differential nonlinearity vs. code 04656-047 0 25000 50000 75000 100000 125000 150000 2059 205a 205b 205c 205d 205e code in hex counts 0 0 131592 129528 0 0 vdd = ref = 5v figure 10. histogram of a dc input at the code transition input level (db) snr reference to full scale (db) 04656-011 80 82 84 86 88 90 ? 1 0? 8? 6? 4? 2 figure 11. snr vs. input level
ad7946 rev. a | page 9 of 24 reference voltage (v) snr, sinad (db) 90.0 87.5 85.0 82.5 80.0 04656-012 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 13.0 13.5 14.0 14.5 15.0 enob (bits) snr sinad enob figure 12. snr, sinad, and enob vs. reference voltage temperature (c) snr (db) 04656-013 80.0 82.5 85.0 87.5 90.0 ?55 ?35 ?15 5 25 45 65 85 105 125 ref = 5v figure 13. snr vs. temperature frequency (khz) sinad (db) 04656-014 70 75 80 85 90 95 100 0 50 100 150 200 ref = 5v, ?10db ref = 5v, ?1db figure 14. sinad vs. frequency sfdr thd reference voltage (v) thd, sfdr (db) 04656-015 ?120 ?115 ?110 ?105 ?100 ?95 ?90 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 figure 15. thd, sfdr vs. reference voltage temperature (c) thd (db) 04656-016 ?130 ?120 ?110 ?100 ? 90 ?55 ?35 ?15 5 25 45 65 85 105 125 ref = 5v figure 16. thd vs. temperature frequency (khz) thd (db) 04656-017 ?120 ?110 ?100 ?90 ?80 ?70 ? 60 0 50 100 150 200 ref = 5v, ?1db ref = 5v, ?10db figure 17. thd vs. frequency
ad7946 rev. a | page 10 of 24 04656-048 0 250 500 750 1000 4.50 4.75 5.00 5.25 5.50 supply (v) oper a ting current (a) vdd vio f s = 100ksps figure 18. operating current vs. supply 04656-050 0 250 500 750 1000 ?55 ?35 ?15 5 25 45 65 85 105 125 temperature (c) power-down current (na) vdd+vio figure 19. power-down current vs. temperature 04656-049 0 250 500 750 1000 ?55 ?35 ?15 5 25 45 65 85 105 125 temperature (c) oper a ting current (a) vdd = 5v vio f s = 100ksps figure 20. operating current vs. temperature temperature (c) offset and gain error (lsb) 04656-021 3 2 1 0 ?1 ?2 ?3 ?55 ?35 ?15 5 25 45 65 85 105 125 offset error gain error figure 21. offset and gain error vs. temperature 0 4 6 5 6 - 0 2 2 sdo capacitive load (pf) 120 0 20406080100 t dsdo delay (ns) 25 20 15 10 5 0 vdd = 5v, 85c vdd = 5v, 25c figure 22. t dsdo delay vs. capacitance load and supply
ad7946 rev. a | page 11 of 24 terminology integral nonlinearity error (inl) inl refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line ( figure 24 ). differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. dnl is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. offset error the first transition should occur at a level ? lsb above analog ground (152.6 v for the 0 v to 5 v range). the offset error is the deviation of the actual transition from that point. gain error the last transition (from 111 10 to 111 11) should occur for an analog voltage 1? lsb below the nominal full scale (4.999542 v for the 0 v to 5 v range). the gain error is the deviation of the actual level of the last transition from the ideal level after the offset has been adjusted out. spurious-free dynamic range (sfdr) sfdr is the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to sinad by the following formula: enob = ( sinad db ? 1.76)/6.02 and is expressed in bits. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in db. signal-to-noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in db. signal-to-(noise + distortion) ratio (sinad) sinad is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for sinad is expressed in db. aperture delay aperture delay is the measurement of the acquisition perform- ance and is the time between the rising edge of the cnv input and when the input signal is held for a conversion. transient resp onse transient response is the time required for the adc to accu- rately acquire its input after a full-scale step function is applied.
ad7946 rev. a | page 12 of 24 theory of operation sw+ msb 4096c 4096c in+ lsb comp control logic switches control busy output code cnv ref gnd in? 4c 2c c c 8192c 8192c sw? msb lsb 4c 2c c c 04656-023 figure 23. adc simplified schematic circuit information the ad7946 is a fast, low power, single-supply, precise 14-bit adc using a successive approximation architecture. the ad7946 can convert 500,000 samples per second (500 ksps) and powers down between conversions. when operating at 100 sps, for example, it consumes 3.3 w typically, ideal for battery-powered applications. the ad7946 provides the user with an on-chip track-and-hold and does not exhibit any pipeline delay or latency, making it ideal for multiple multiplexed channel applications. the ad7946 is specified from 4.5 v to 5.5 v and can be interfaced to any of the 1.8 v to 5 v digital logic family. it is housed in a 10-lead msop or a tiny 10-lead qfn (lfcsp) that combines space savings and allows flexible configurations. it is pin-for-pin compatible with the 16-bit adc ad7686 . converter operation the ad7946 is a successive approximation adc based on a charge redistribution dac. figure 23 shows the simplified schematic of the adc. the capacitive dac consists of two identical arrays of 14 binary weighted capacitors, which are connected to the two comparator inputs. during the acquisition phase, the terminals of the array that are tied to the comparators input are connected to gnd via sw+ and sw?. all independent switches are connected to the analog inputs. thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the in+ and in? inputs. when the acquisition phase is complete and the cnv input goes high, a conversion phase is initiated. when the conversion phase begins, sw+ and sw? are opened first. the two capacitor arrays are then disconnected from the inputs and connected to the gnd input. therefore, the differential voltage between the inputs in+ and in? captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array between gnd and ref, the comparator input varies by binary weighted voltage steps (ref/2, ref/4 ref/16,384). the control logic toggles these switches, starting with the msb, in order to bring the comparator back into a balanced condition. after completing this process, the part returns to the acquisition phase, and the control logic generates the adc output code and a busy signal indicator. because the ad7946 has an on-board conversion clock, the serial clock, sck, is not required for the conversion process. transfer functions the ideal transfer characteristic for the ad7946 is shown in figure 24 and table 7 . 000...000 000...001 000...010 111...101 111...110 111...111 adc code (straight binary) analog input +fsr ? 1.5 lsb +fsr ? 1 lsb ?fsr + 1 lsb ?fsr ?fsr + 0.5 lsb 04656-024 figure 24. adc ideal transfer function tale 7. output codes and ideal input voltages description analog input ref = 5 v digital output code hexa fsr ? 1 lsb 4.999695 v 3fff 1 midscale + 1 lsb 2.500305 v 2001 midscale 2.5 v 2000 midscale ? 1 lsb 2.499695 v 1fff ?fsr + 1 lsb 305.2 v 0001 ?fsr 0 v 0000 2 1 this is also the code for an overranged analog input (v in+ ? v in? above ref ? v gnd ). 2 this is also the code for an underranged analog input (v in+ ? v in? below v gnd ).
ad7946 rev. a | page 13 of 24 typical connection diagram figure 25 shows an example of the recommended connection diagram for the ad7946 when multiple supplies are available. ad7946 ref gnd vdd in? in+ vio sdi sck sdo cnv 3- or 4-wire interface (note 5) 100nf 100nf 5v 10 f (note 2) v+ v+ v? 1.8v to vdd ref 0v to ref 33 ? 2.7nf 04656-025 notes 1. see reference section for reference selection. 2 . c ref is usually a 10 f ceramic capacitor (x5r). 3 . see drive r amplifier choice section. 4 . option a l filter. see analog input section. 5. see digital interface for most convenient interface mode. (note 1) (ada4841 or note 3) (note 4) figure 25. typical application diagram with multiple supplies analog input figure 26 shows an equivalent circuit of the input structure of the ad7946. the two diodes, d1 and d2, provide esd protection for the analog inputs in+ and in?. care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 v because this causes these diodes to begin to forward- bias and start conducting current. these diodes can handle a maximum forward-biased current of 130 ma. for instance, these conditions could eventually occur when the input buffers (u1) supplies are different from vdd. in such a case, an input buffer with a short-circuit current limitation can be used to protect the part. c in r in d1 d2 c pin in+ or in? gnd vdd 04656-026 figure 26. equivalent analog input circuit the analog input structure allows the sampling of the differential signal between in+ and in?. by using this differential input, small signals common to both inputs are rejected, as shown in figure 27 , which represents the typical cmrr over frequency. for instance, by using in? to sense a remote signal ground, ground potential differences between the sensor and the local adc ground are eliminated. frequency (khz) cmrr (db) 04656-027 50 40 60 70 10 1 100 1k 10k vdd = 5v figure 27. analog input cmrr vs. frequency during the acquisition phase, the impedance of the analog inputs (in+ or in?) can be modeled as a parallel combination of capacitor, c pin , and the network formed by the series connec- tion of r in and c in . c pin is primarily the pin capacitance. r in is typically 600 and is a lumped component made up of some serial resistors and the on resistance of the switches. c in is typically 30 pf and is mainly the adc sampling capacitor. during the conversion phase, when the switches are opened, the input impedance is limited to c pin . r in and c in make a 1-pole, low-pass filter, which reduces undesirable aliasing effects and limits the noise. when the source impedance of the driving circuit is low, the ad7946 can be driven directly. large source impedances significantly affect the ac performance, especially total harmonic distortion (thd). the dc performances are less sensitive to the input impedance. the maximum source impedance depends on the amount of thd that can be
ad7946 rev. a | page 14 of 24 tolerated. the thd degrades as a function of the source impedance and the maximum input frequency, as shown in figure 28 . frequency (khz) thd (db) 04656-028 ?105 ?110 ?100 ?90 ?95 ?85 ? 80 0 2 55 07 5 1 0 0 r s = 33 ? r s = 50 ? r s =100 ? r s = 250 ? figure 28. thd vs. analog input frequency and source resistance driver amplifier choice although the ad7946 is easy to drive, the driver amplifier needs to meet the following requirements: ? the noise generated by the driver amplifier needs to be kept as low as possible to preserve the snr and transition noise performance of the ad7946. note that the ad7946 has a noise much lower than most of the other 14-bit adcs and, therefore, can be driven by a noisier amplifier to meet a given system noise specification. the noise coming from the amplifier is filtered by the ad7946 analog input circuit 1-pole, low-pass filter made by r in and c in or by the external filter, if one is used. ? for ac applications, the driver should have a thd perform- ance commensurate with the ad7946. figure 17 shows the thd vs. frequency that the driver should exceed. ? for multichannel multiplexed applications, the driver amplifier and the ad7946 analog input circuit must settle a full-scale step onto the capacitor array at a 14-bit level (0.006%). in the amplifiers data sheet, settling at 0.1% to 0.01% is more commonly specified. this could differ significantly from the settling time at a 14-bit level and should be verified prior to driver selection. table 8. recommended driver amplifiers amplifier typical application ada4841 very low noise, small and low power ad8021 very low noise and high frequency ad8655 5 v single-supply, low noise, and low power ad8022 low noise and high frequency op184 low power, low noise, and low frequency ad8605 , ad8615 5 v single-supply, low power ad8519 small, low power, and low frequency ad8031 high frequency and low power voltage reference input the ad7946 voltage reference input ref has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the ref and gnd pins, as explained in the layout section. when ref is driven by a very low impedance source, for example, a reference buffer using the ad8031 or the ad8603 , a 10 f (x5r, 0805 size) ceramic chip capacitor is appropriate for optimum performance. if an unbuffered reference voltage is used, the decoupling value depends on the reference used. for instance, a 22 f (x5r, 1206 size) ceramic chip capacitor is appropriate for optimum performance using a low temperature drift adr43x reference. if desired, smaller reference decoupling capacitor values down to 2.2 f can be used with a minimal impact on performance, especially dnl. regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nf) between the ref and gnd pins.
ad7946 rev. a | page 15 of 24 power supply the ad7946 is specified at 4.5 v to 5.5 v. it uses two power supply pins: a core supply vdd and a digital input/output interface supply vio. vio allows direct interface with any logic between 1.8 v and vdd. to reduce the supplies needed, the vio and vdd can be tied together. the ad7946 is independent of power supply sequencing between vio and vdd. additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in figure 29 , which represents psrr over frequency. frequency (khz) psrr (db) 04656-029 50 40 30 60 90 80 70 10 1 100 1k 10k vdd = 5v figure 29. psrr vs. frequency the ad7946 powers down automatically at the end of each conversion phase and, therefore, the power scales linearly with the sampling rate, as shown in figure 30 . this makes the part ideal for low sampling rate (even a few hz) and low battery- powered applications. 04656-051 0.001 0.1 1 0.01 10 100 1000 10 100 1k 10k 100k 1m sampling rate (sps) oper a ting current (a) vio vdd = 5v figure 30. operating currents vs. sampling rate supplying the adc from the reference for simplified applications, the ad7946, with its low operating current, can be supplied directly using the reference circuit shown in figure 31 . the reference line can be driven by one of the following: ? the system power supply directly. ? a reference voltage with enough current output capability, such as the adr43x. ? a reference buffer, such as the ad8031 or ad8603 , which can also filter the system power supply, as shown in figure 31 . ad8603 ad7946 vio ref (note 1) vdd 10f 1f 10k ? 1k ? 47k ? 5v 5v 1f 04656-031 notes 1. optional reference buffer and filter figure 31. example of application circuit single-supply application figure 32 shows a typical 14-bit single-supply application. there are different challenges to doing a single-supply, high resolution design, and the ada4841 addresses these nicely. the combina- tion of low noise, low power, wide input range, rail-to-rail output, and high speed make the ada4841 a perfect driver solution for low power, single-supply 14-bit adcs, such as the ad7946. in a single-supply system, one of the main challenges is to use the amplifier in buffer mode to have the lowest output noise and still preserve linearity compatible with the adc. rail-to-rail input amplifiers usually have higher noise than the ada4841 and cannot be used on their entire input range in buffer mode because of the nonlinear region around the crossover point of their input stage. the ada4841, which has no crossover region but has a wide linear input range from ground to 1 v below positive rail, solves this issue, as shown in figure 32 , where it can accept the 0 v to 4.096 v input range with a supply as low as 5.2 v. this supply allows using a small, low dropout, low temperature drift adr364 reference voltage. note that, like any rail-to-rail output amplifier at the low end of its output range close to ground, the ada4841 can exhibit some nonlinearity on a small region of approximately 25 mv from ground. the ada4841 drives a 1-pole, low-pass filter. this filter limits the already very low noise contribution from the amplifier to the ad7946.
ad7946 rev. a | page 16 of 24 ad7946 ref gnd vdd in? in+ vio sdi sck sdo cnv 100nf 10f adr364 33 ? 2.7nf 0v to 4.096v ada4841 100nf >5.2 v 100nf 04656-052 figure 32. example of a sing le-supply application circuit digital interface although the ad7946 has a reduced number of pins, it offers flexibility in its serial interface modes. the ad7946, when in cs mode, is compatible with spi, qspi?, digital hosts, and dsps, for example, blackfin? adsp-bf53x or adsp-219x. this interface can use either 3-wire or 4-wire. a 3-wire interface using the cnv, sck, and sdo signals mini- mizes wiring connections useful, for instance, in isolated applications. a 4-wire interface using the sdi, cnv, sck, and sdo signals allows cnv, which initiates the conversions, to be independent of the readback timing (sdi). this is useful in low jitter sampling or simultaneous sampling applications. the ad7946, when in chain mode, provides a daisy chain feature using the sdi input for cascading multiple adcs on a single data line similar to a shift register. the operating mode depends on the sdi level when the cnv rising edge occurs. cs mode is selected if sdi is high, and chain mode is selected if sdi is low. the sdi hold time is such that when sdi and cnv are connected, the chain mode is always selected. in either mode, the ad7946 offers the flexibility to optionally force a start bit in front of the data bits. this start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading. otherwise, without a busy indicator, the user must time out the maximum conversion time prior to readback. busy indicator feature is enabled ? in cs mode, if cnv or sdi is low when the adc conversion ends (see figure 36 and figure 40 ). ? in chain mode, if sck is high during the cnv rising edge (see figure 44 ).
ad7946 rev. a | page 17 of 24 cs mode 3-wire, no busy indicator this mode is usually used when a single ad7946 is connected to an spi-compatible digital host. the connection diagram is shown in figure 33 and the corresponding timing is given in figure 34 . with sdi tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. once a conversion is initiated, it continues to completion irrespective of the state of cnv. for instance, it could be useful to bring cnv low to select other spi devices, such as analog multiplexers, but cnv must be returned high before the minimum conversion time and held high until the maximum conversion time to avoid the generation of the busy signal indicator. when the conversion is complete, the ad7946 enters the acquisition phase and powers down. when cnv goes low, the msb is output onto sdo. the remaining data bits are then clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the 14 th sck falling edge or when cnv goes high, whichever is earlier, sdo returns to high impedance. cnv sck sdo sdi data in clk convert v io digital host ad7946 04656-032 figure 33. cs mode 3-wire, no busy indicator connection diagram (sdi high) sdo d13 d12 d11 d1 d0 t dis sck 123 121314 t sck t sckl t sckh t hsdo t dsdo cnv conversion acquisition t conv t cyc acquisition sdi = 1 t cnvh t acq t en 04656-033 figure 34. cs mode 3-wire, no busy indicator serial interface timing (sdi high)
ad7946 rev. a | page 18 of 24 cs mode 3-wire with busy indicator this mode is usually used when a single ad7946 is connected to an spi-compatible digital host having an interrupt input. the connection diagram is shown in figure 35 , and the corresponding timing is given in figure 36 . with sdi tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. sdo is maintained in high impedance until the completion of the conversion irrespective of the state of cnv. prior to the minimum conversion time, cnv could be used to select other spi devices, such as analog multiplexers, but cnv must be returned low before th e minimum conversion time and held low until the maximum conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high impedance to low. with a pull-up on the sdo line, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. the ad7946 then enters the acquisition phase and powers down. the data bits are then clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the optional 15 th sck falling edge, or when cnv goes high, whichever is earlier, sdo returns to high impedance. if multiple ad7946s are selected at the same time, the sdo output pin handles this contention without damage or induced latch-up. meanwhile, it is recommended to keep this contention as short as possible to limit extra power dissipation. data in irq clk convert vio digital host 04656-034 47k ? cnv sck sdo sdi v io ad7946 figure 35. cs mode 3-wire with busy indicator connection diagram (sdi high) sdo d13 d12 d1 d0 t dis sck 123 131415 t sck t sckl t sckh t hsdo t dsdo cnv conversion acquisition t conv t cyc t cnvh t acq acquisition sdi = 1 04656-035 figure 36. cs mode 3-wire with busy indicator serial interface timing (sdi high)
ad7946 rev. a | page 19 of 24 cs mode 4-wire, no busy indicator this mode is usually used when multiple ad7946s are connected to an spi-compatible digital host. a connection diagram example using two ad7946s is shown in figure 37 , and the corresponding timing is given in figure 38 . with sdi high, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data readback (if sdi and cnv are low, sdo is driven low). prior to the minimum conversion time, sdi could be used to select other spi devices, such as analog multiplexers, but sdi must be returned high before the minimum conversion time and held high until the maximum conversion time to avoid the generation of the busy signal indicator. when the conversion is complete, the ad7946 enters the acquisition phase and powers down. each adc result can be read by bringing its sdi input low, which consequently outputs the msb onto sdo. the remaining data bits are then clocked by subse- quent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the 14 th sck falling edge, or when sdi goes high, whichever is earlier, sdo returns to high impedance and another ad7946 can be read. data in clk cs1 convert cs2 digital host 04656-036 cnv sck sdo sdi ad7946 cnv sck sdo sdi ad7946 figure 37. cs mode 4-wire, no busy in dicator connection diagram sdo d13 d12 d11 d1 d0 t dis sck 123 262728 t hsdo t dsdo t en conversion acquisition t conv t cyc t acq acquisition sdi(cs1) cnv t ssdicnv t hsdicnv d1 12 13 t sck t sckl t sckh d0 d13 d12 15 16 14 sdi(cs2) 04656-037 figure 38. cs mode 4-wire, no busy indicator serial interface timing
ad7946 rev. a | page 20 of 24 cs mode 4-wire with busy indicator this mode is usually used when a single ad7946 is connected to an spi-compatible digital host, which has an interrupt input, and it is desired to keep cnv, which is used to sample the analog input, independent of the signal used to select the data reading. this requirement is particularly important in applications where low jitter on cnv is desired. the connection diagram is shown in figure 39 , and the corresponding timing is given in figure 40 . with sdi high, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data readback (if sdi and cnv are low, sdo is driven low). prior to the minimum conversion time, sdi could be used to select other spi devices, such as analog multiplexers, but sdi must be returned low before the minimum conversion time and held low until the maximum conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high impedance to low. with a pull-up on the sdo line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. the ad7946 then enters the acquisition phase and powers down. the data bits are then clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the optional 15 th sck falling edge or sdi going high, whichever is earlier, the sdo returns to high impedance. data in irq clk convert vio digital host 04656-038 47k ? cnv sck sdo sdi ad7946 cs1 figure 39. cs mode 4-wire with busy indicator connection diagram sdo d13 d12 d1 d0 t dis sck 123 131415 t sck t sckl t sckh t hsdo t dsdo t en conversion acquisition t conv t cyc t acq acquisition sdi cnv t ssdicnv t hsdicnv 04656-039 figure 40. cs mode 4-wire with busy indicator serial interface timing
ad7946 rev. a | page 21 of 24 chain mode, no busy indicator this mode can be used to daisy-chain multiple ad7946s on a 3-wire serial interface. this feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. data readback is analogous to clocking a shift register. a connection diagram example using two ad7946s is shown in figure 41 , and the corresponding timing is given in figure 42 . when sdi and cnv are low, sdo is driven low. with sck low, a rising edge on cnv initiates a conversion, selects the chain mode, and disables the busy indicator. in this mode, cnv is held high during the conversion phase and the subsequent data readback. when the conversion is complete, the msb is output onto sdo, and the ad7946 enters the acquisition phase and powers down. the remaining data bits stored in the internal shift register are then clocked by subsequent sck falling edges. for each adc, sdi feeds the input of the internal shift register and is clocked by the sck falling edge. each adc in the chain outputs its data msb first, and 14 n clocks are required to readback the n adcs. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate and consequently more ad7946s in the chain, provided the digital host has an acceptable hold time. the maximum conver- sion rate may be reduced due to the total readback time. for instance, with a 3 ns digital host setup time and 3 v interface, up to four ad7946s running at a conversion rate of 360 ksps can be daisy-chained on a 3-wire port. clk convert data in digital host 04656-040 cnv sck sdo sdi ad7946 b cnv sck sdo sdi ad7946 a figure 41. chain mode, no busy indicator connection diagram sdo a = sdi b d a 13 d a 12 d a 11 sck 1 2 3 262728 t ssdisck t hsdisck t en conversion acquisition t conv t cyc t acq acquisition cnv d a 1 12 13 t sck t sckl t sckh d a 0 15 16 14 sdi a = 0 sdo b d b 13 d b 12 d b 11 d a 1 d b 1d b 0d a 13 d a 12 t hsdo t dsdo t ssckcnv t hsckcnv d a 0 04656-041 figure 42. chain mode, no busy indicator serial interface timing
ad7946 rev. a | page 22 of 24 chain mode with busy indicator this mode can be used to daisy-chain multiple ad7946s on a 3-wire serial interface while providing a busy indicator. this feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. data readback is analogous to clocking a shift register. a connection diagram example using three ad7946s is shown in figure 43 , and the corresponding timing is given in figure 44 . when sdi and cnv are low, sdo is driven low. with sck high, a rising edge on cnv initiates a conversion, selects the chain mode, and enables the busy indicator feature. in this mode, cnv is held high during the conversion phase and the subsequent data readback. when all adcs in the chain have completed their conversions, the near-end adc (adc c in figure 43 ) sdo is driven high. this transition on sdo can be used as a busy indicator to trigger the data readback controlled by the digital host. the ad7946 then enters the acquisition phase and powers down. the data bits stored in the internal shift register are then clocked out, msb first, by subsequent sck falling edges. for each adc, sdi feeds the input of the internal shift register and is clocked by the sck falling edge. each adc in the chain outputs its data msb first, and 14 n + 1 clocks are required to readback the n adcs. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate and consequently more ad7946s in the chain, provided the digital host has an acceptable hold time. for instance, with a 3 ns digital host setup time and 3 v interface, up to four ad7946s running at a conversion rate of 360 ksps can be daisy-chained to a single 3-wire port. clk convert data in irq digital host 04656-042 cnv sck sdo sdi ad7946 c cnv sck sdo sdi ad7946 a cnv sck sdo sdi ad7946 b figure 43. chain mode with bu sy indicator connection diagram sdo a = sdi b d a 13 d a 12 d a 11 sck 123 31 41 42 t en conversion acquisition t conv t cyc t acq acquisition cnv = sdi a d a 1 413 t sck t sckh t sckl d a 0 15 30 14 sdo b = sdi c d b 13 d b 12 d b 11 d a 1 d b 1d b 0d a 13 d a 12 43 t ssdisck t hsdisck t hsdo t dsdo sdo c d c 13 d c 12 d c 11 d a 1d a 0 d c 1d c 0d a 12 17 27 28 16 29 d b 1d b 0d a 13 d b 13 d b 12 t dsdosdi t ssckcnv t hsckcnv 0 4656-043 d a 0 t dsdosdi t dsdosdi t dsdosdi t dsdosdi figure 44. chain mode with busy indicator serial interface timing
ad7946 rev. a | page 23 of 24 application guidelines layout the printed circuit board that houses the ad7946 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. the pinout of the ad7946, with all its analog signals on the left side and all its digital signals on the right side, eases this task. avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the ad7946 is used as a shield. fast switching signals, such as cnv or clocks, should never run near analog signal paths. crossover of digital and analog signals should be avoided. at least one ground plane should be used. it could be common or split between the digital and analog sections. in the latter case, the planes should be joined underneath the ad7946s. the ad7946 voltage reference input ref has a dynamic input impedance and should be decoupled with minimal parasitic inductances. this is done by placing the reference decoupling ceramic capacitor close to, and ideally right up against, the ref and gnd pins and connecting it with wide, low impedance traces. finally, the power supplies vdd and vio of the ad7946 should be decoupled with ceramic capacitors (typically 100 nf) placed close to the ad7946 and connected using short and wide traces to provide low impedance paths and reduce the effect of glitches on the power supply lines. an example of layout following these rules is shown in figure 45 and figure 46 . evaluating the ad7946s performance other recommended layouts for the ad7946 are outlined in the documentation of the evaluation board for the ad7946 (eval-ad7946cb). the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the eval-control brd3. 04656-044 figure 45. example of layout of the ad7946 (top layer) 04656-045 figure 46. example of layout of the ad7946 (bottom layer)
ad7946 rev. a | page 24 of 24 outline dimensions compliant to jedec standards mo-187-ba 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.05 0.33 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc pin 1 coplanarity 0.10 3.10 3.00 2.90 3.10 3.00 2.90 5.15 4.90 4.65 figure 47.10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters 101207-b top view 10 1 6 5 0.30 0.23 0.18 * exposed pad (bottom view) pin 1 index area 3.00 bsc sq seating plane 0.80 0.75 0.70 0.20 ref 0.05 max 0.02 nom 0.80 max 0.55 nom 1.74 1.64 1.49 2.48 2.38 2.23 0.50 0.40 0.30 0.50 bsc p i n 1 i n d i c a t o r ( r 0 . 1 9 ) * paddle connected to gnd. this connection is not required to meet the electrical performances figure 48. 10-lead lead frame chip scale package [qfn (lfcsp_wd)] 3 mm 3 mm body, very very thin, dual lead (cp-10-9) dimensions shown in millimeters ordering guide model temperature range package description pa ckage option ordering quantity branding ad7946brm ?40c to +85c 10-lead msop rm-10 tube, 50 c1e ad7946brm-rl7 ?40c to +85c 10-lead msop rm-10 reel, 1,000 c1e ad7946brmz 1 ?40c to +85c 10-lead msop rm-10 tube, 50 c4x ad7946brmzrl7 1 ?40c to +85c 10-lead msop rm-10 reel, 1,000 c4x ad7946bcpzrl7 1 ?40c to +85c 10-lead qfn (lfcsp_wd) cp-10-9 reel, 1,000 c4x ad7946bcpzrl 1 ?40c to +85c 10-lead qfn (lfcsp_wd) cp-10-9 reel, 5,000 c4x eval-ad7946cbz 1 , 2 evaluation board eval-control brd3z 1 , 3 evaluation board t 1 z = rohs compliant part. 2 this board can be used as a standalone evaluation board or in conjunction with the eval-control brd3z for evaluation/demonstra tion purposes. 3 this board allows a pc to control and communicate with all analog devices, inc. evaluation boards ending in the cb designator. ?2005C2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04656-0-12/07(a) ttt

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